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Up Topic Rybka Support & Discussion / Rybka Discussion / FPGA cards and RYBKA
- - By albitex (***) Date 2007-07-11 19:45
I have read that Dr Christian Donninger has used some cards FPGA to increase the speed of analysis with the engines. In practice these cards, relieve the job of the CPU during the calculation of the variations.
I have also read that some new display adapters, are costuite with a GPU that works
from ALU (Unity Arimetic Logic), that can be used for helping the CPU of the system to perform the calculations.
Has someone tried to use these cards with Rybka?
I attach file of description cards FPGA.
Does someone know how to tell more me something on these cards and their use for the chess engine ?
Attachment: FPGA.htm (13k)
Parent - - By Vasik Rajlich (Silver) Date 2007-07-12 07:41
FWIW - Chrilly claimed a 5x speedup from use of the card. This value will depend on a number of factors, one being state of FPGA vs state of CPUs.

Vas
Parent - - By albitex (***) Date 2007-07-14 21:03
Vas. I have written to the Alpha Data to have information on the cards FPGA.
But me, to today , I have not had anybody answer.
I would like to know, where and as to purchase the cards. And their price.
I would like to try her with Rybka.
I am partner of the circle of chess S.S.T. , circle in Turin.
The president (Michael Cordara)  he has been the organizer of the 2006 Olympiads of
chess, and I know the dott Fresco, he is  ex administrator Fiat and
impassioned of chess (one of the principal promoting of the Olympiads).
I would like to propose to them, an application to get a financing for
to build a computer, with quad core + FPGA, with Rybka. But I don't have anything
in hand. I should have documentation, illustrative sheets etc..
I want to do something, but not there and a lot of biography on the matter.
Hi Alberto
Parent - - By Vasik Rajlich (Silver) Date 2007-07-16 10:32
Hi,

it would take a lot of work to adapt Rybka to an FPGA. This work would have to be (potentially) re-done when the next generation of FPGA cards became available. In addition, the price of each Rybka would be around 500 Euro per card. For an 8-core machine, we're looking at 4,000 Euro, which is a bit expensive. I doubt whether we'll ever do this.

Vas
Parent - - By M ANSARI (*****) Date 2007-07-16 12:32
Hydra is based of FPGA cards running at around 30Mhz ... or maybe 50Mhz (depending on which model FPGA they are using).  Today those cards run at 65nm and speed is 133Mhz (if not faster).  This mated with the fact that Core 2 Xeon processors are much more powerful and have 4 cores each ... would probably show that Hydra is acutally on outdated hardware.  Hardware is obviously very important for chess engines ... the more power you have the deeper you can look into a position.  But while critical in tactical positions, you would still have to evaluate correctly the position you searched deeply.  If that evaluation turns out to be inaccurate, then another engine running a more accurate evaluation will win even with a hardware deficit.  I think Rybka would have very good chances to beat Hydra even with much inferior hardware.  I remember that Shredder 9 was beaten much less handily than today's Rybka with today's hardware would.  A good example where evaluation is important was in the last computer chess championship between Rybka and Zappa.  Rybka went into a line where Zappa and Hiarcs saw as 0.00 ... while Rybka saw a +1.00 advantage.  It turned out that Rybka's evaluation was actually correct (although Rybka did not win the game due to lack of EGTB's).  So Hydra could easily search a position much more deeply than Rybka and evaluate it as better while it actually is worse.

Having said that it is very obvious that a Rybka on a Hydra type hardware would perform at a much better level than today's best Rybka.  But the big question is what is the best and most promising avenue for hardware.  Is FPGA really the way to go .... is maybe better software parallelism on today's existing Workstation a better option ... or is a multi board cluster system more promising?  This will have to be decided by Vas ...  Personally I think the best option is a combination of better parallelism code using multi board system (type of cluster).
Parent - - By turbojuice1122 (Gold) Date 2007-07-16 16:24
I don't think you can really make any statements based on the match between Hydra and Shredder 8 sometime ago.  First, Shredder 8 (this was the version used, not Shredder 9) has extremely good scaling with multiple processors, so good that the old Shredder 8 on 4 CPU's is probably at least as good as Deep Shredder 10 on 4 CPU's (and it might even be better).  Second, you cannot draw conclusions based on 8 games, as I'm sure you know.  I think if you make a long match between Rybka and Shredder, you will find an 8-game stretch where Shredder has a positive score.  Third, Hydra was only using 16 CPU's in that match.
Parent - By Vempele (Silver) Date 2007-07-16 17:01

> First, Shredder 8 (this was the version used, not Shredder 9)


Incorrect! It was a buggy intermediate version (apparently, an important piece of code was accidentally deleted. Sandro Necchi (author of Shredder's openings book) said it was 150 points weaker than Shredder 9). Shredder played a 1-move blunder (losing a bishop IIRC) in one of the games, for example.

Thus confirming your point beyond reasonable doubt.
Parent - By albitex (***) Date 2007-07-16 22:48
M Ansari you are probably right when you sustain that the cards FPGAs are old
and a dual XENON and more powerful  of a CPU strengthened with FPGA.
But I am interested to the principle of operation. To the idea of Donninger.
In practice he has used the cards FPGA, to relieve the job of the CPU, in way of
to get a speed of greater analysis. In practice he has transformed, a CPU general porpouse,
in a CPU devoted (risc).
Today perhaps the cards FPGA are old to be used on the multicores, but there are surely
or we can be invented, anything that accelerates the job of the CPU in the analysis of chess.
I have to document me. But I am sure that anything can be done.
Thanks of the attention
Parent - - By Vasik Rajlich (Silver) Date 2007-07-18 07:31
The other thing to keep in mind that the more malleable your medium, the faster you can move ahead. Overall, I see it as no contest in favor of software.

Vas
Parent - By albitex (***) Date 2007-07-18 17:38
www.macs.ece.mcgill.ca/~mboul/CICCpaper.pdf
This a link for FPGA .
title for search on google : An FPGA Move Generator for the Game of Chess 5
Parent - By albitex (***) Date 2007-07-18 17:30
An FPGA Move Generator for the Game of Chess 5

As a result, the chess square circuit does not require two transmitters and double-input receivers. When compared to
the DEEP BLUE move generator, the amount of connections between chess squares is reduced by 17.6%. During
normal find-victim and find-aggressor cycles, input piece color is unnecessary. However, during the find-pivot
cycle, opposing colors that align properly on the pivot square will indicate a checking move. This representation also
creates a more uniform interconnect pattern and maximizes information distribution. The find-check operation is
therefore a find-pivot cycle followed by a find-aggressor cycle.
5. IMPLEMENTATION AND RESULTS
The FPGA design was done in VHDL (a Hardware Description Language) and the chess program was coded in C.
The chip used is an XCV800-4 and the implementation tools are by Xilinx. A device driver interfaces the FPGA
mounted on a PCI card to the chess software. The Peripheral Component Interconnect (PCI) standard is the main bus
architecture used in personal computers (see the Appendix). A C program was created to generate the VHDL file
responsible for interconnecting 64 instances of chess squares and 63 instances of arbiters. Location constraints were
also generated with this program and were used to inform the place-and-route tool that the chessboard is an 8×8
array. This reduces implementation time and produces a design with better performance. In this case, a 17% speed

An FPGA Move Generator for the Game of Chess

increase was obtained. The entire design uses approximately 10 100 LUTs, 350 32x1RAMs, 800 flip-flops and runs
at 33 MHz. Because of the large amount of combinatorial delays involved in propagating signals from one side of
the board (chip) to the other, the find-victim, find-pivot and find-aggressor instructions have a duration of three
cycles in the chess state machine. For simplicity, the move generator and its state machine are clocked at the PCI bus
frequency.

The chess move generator also includes a PCI interface to connect it to the computer running MBCHESS. Many
different commands allow the communication overhead to be diminished. For example, in a single read from the
card, the move generator can be instructed to unmake the currently stored move, generate and return the next move
and execute that move on its hardware chessboard. This simultaneous write-and-read is possible when part of the
address is used to pass a command rather than address memory locations. The chess state machine has all the
necessary controls to make and unmake all types of moves. Table 2 presents results obtained for a 33 MHz clock
frequency. The FPGA move generator can return approximately 1.4 million pseudo-legal moves per second and
900,000 legal moves per second to a test program running on the host processor. Further accounting for the software
overhead in maintaining a soft-copy (local copy) of the chessboard, a skeleton alpha-beta algorithm operates at
roughly 280,000 positions per second. Using the same settings (alpha-beta with checks first), the un-accelerated
version of MBCHESS searches roughly 50,000 positions per second (450 MHz AMD processor). By itself (excluding
PCI communication overhead and simple clocking scheme), the FPGA move generator can operate at approximately

Source:
1 McGill University, Department of Electrical Engineering, McConnell Engineering Building Room 633, 3480 University Street,
Montreal, Quebec, Canada, H3A 2A7. Email: {mboul,zeljko}@macs.ece.mcgill.ca
Parent - By albitex (***) Date 2007-07-16 22:59 Edited 2007-07-16 23:01
Vas. I have to document me. But I am sure that a way hardware exists for increasing the speed of the CPU in the analysis of chess.
I will now make you know if I get some result.
I think about September. You have to know that in Italy, to August, it jams everything for the vacations.
To hear again us.
Hi Alberto
Up Topic Rybka Support & Discussion / Rybka Discussion / FPGA cards and RYBKA

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